1. Field of the Invention
The present invention relates to a resin-encapsulated semiconductor device, in particular, to a semiconductor device having a structure in which a lead for connection to a circuit board and an island for mounting a semiconductor chip thereon are exposed from a mold resin.
2. Description of the Related Art
Various electronic devices, including portable devices, are becoming thinner, smaller, and lighter. Semiconductor packages to be mounted on the electronic devices are also required to be thinner and smaller. Thinning and downsizing of the semiconductor package cannot be achieved by a related-art gullwing type semiconductor package. It is thus effective to employ a so-called flat package, in which lead ends are flat and a bottom surface of the semiconductor package and a bottom surface of the lead are level with each other.
The basic structure of the flat package is that a lead for connection to a circuit board is exposed from a rear surface of the package, which is a surface to be mounted on the circuit board. Further, an island is exposed from the rear surface of the package in some cases and not in other cases. The lead bottom surface and the package bottom surface are flat, and hence, when the package is mounted on the circuit board by solder, the solder comes into contact with a mold resin at the lead bottom surface and at the package bottom surface.
FIG. 18 illustrates a related-art semiconductor package. A bottom surface of a lead 1, a bottom surface of a mold resin 6, and a bottom surface of an island 3 are flush with one another.
The basic structure of the flat package is disclosed in Japanese Published Patent Application Nos. 2000-299400 and 2009-060093.
In the related-art structure, however, when the semiconductor package is mounted on the circuit board, the solder printed on the circuit board and the bottom surface of the mold resin are brought into contact with each other, and hence there is a problem in that the self-alignment property that automatically corrects a misalignment of the semiconductor package when the solder melts is reduced. When bonding alignment between the circuit board and the semiconductor package is lost, an effective bonding area between the lead of the semiconductor package and the solder printed on the circuit board is reduced to decrease mounting strength.